[Ipsaus-adlc] Simulador de segmentación de MIPS
Gilgamezh
gilgamezh en gmail.com
Jue Jun 9 04:37:21 CEST 2011
copado el simulador este para hacer pruebas con las 5 etapas de
segmentación de MIPS.
saludos
Nico
http://www.ecs.umass.edu/ece/koren/architecture/windlx/main.html
Overview
This application is a partial simulation of a MIPS Five Stage Pipeline.
The user can pick from a limited number of assembly instructions to be
executed in the pipeline. Instructions in the pipeline are checked for
"possible" data and structural hazards before execution. During
execution, the instructions can be stepped through the stages of the
pipeline one cycle at a time, or the final results can be displayed
instantly. The display shows where stalls have occurred in the pipeline.
Data forwarding can be enabled or disabled.
The simulation does not allow the user to insert specific values into
the registers and does not compute the actual result of any of the
instructions. This is simply a tool that should be used to detect
possible data and structural hazards and to view instructions as they
are executed on a five stage MIPS pipeline.
Instructions are issued "in-order" so WAR hazards can never occur while
the instructions are being executed. However, WAR hazards are listed
under the "Potential Hazards" for completeness.
It is assumed that there is a sperate data cache and instruction cache
so that stalls will never occur due to an instruction being read from
memory at the same time as a piece of data is being read from or written
to memory.
Registers
The simulation supports 16 Floating-Point Registers (R1 - R16) and 32
Integer Registers (F1 - F32).
Assembly Instructions
The following assembly instructions are supported:
FP_Add(dest, src1, src2)
The floating-point add instruction adds the two source registers and
stores the result in the destination register. This instruction can take
from 1 - 20 cycles to complete execution. The execution time is
selectable by the user and is always the same as the FP_Sub instruction.
FP_Sub(dest, src1, src2)
The floating-point subtract instruction subtracts the two source
registers and stores the result in the destination register. This
instruction can take from 1 - 20 cycles to complete execution. The
execution time is selectable by the user and is always the same as the
FP_Add instruction.
FP_Mult(dest, src1, src2)
The floating-point multiply instruction multiplies the two source
registers and stores the result in the destination register. This
instruction can take from 1 - 20 cycles to complete execution. The
execution time is selectable by the user.
FP_Div(dest, src1, src2)
The floating-point divide instruction divides the two source registers
and stores the result in the destination register. This instruction can
take from 1 - 20 cycles to complete execution. The execution time is
selectable by the user.
FP_Load(dest, offset, src1)
The floating-point load instruction uses an integer value stored in
source register # 1 and an offset to compute the memory address from
which data will be loaded into the destination register. This
instruction takes 1 cycle during the execution stage to compute the
memory address. The value from memory is available after the MEM stage.
It is assumed that the requested data is always available in the data
cache so that the pipeline will never have to stall while data is read
from the memory.
FP_Store(src1, offset, src2)
The floating-point store instruction uses an integer value stored in
source register # 2 and an offset to compute the memory address to which
the data in source register # 1 will be stored. This instruction takes 1
cycle during the execution stage to compute the memory address. The
value is written to memory by the end of the MEM stage. It is assumed
that the data to be written to memory is already available in the data
cache so that the pipeline will never have to stall while data is
written to memory. This instruction does not go through the WB stage.
INT_Add(dest, src1, src2)
The integer add instruction adds the two source registers and stores the
result in the destination register. This instruction takes 1 cycle to
complete execution.
INT_Sub(dest, src1, src2)
The integer subtract instruction subtracts the two source registers and
stores the result in the destination register. This instruction takes 1
cycle to complete execution.
INT_Mult(dest, src1, src2)
The integer multiply instruction multiplies the two source registers and
stores the result in the destination register. This instruction takes 1
cycle to complete execution.
INT_Div(dest, src1, src2)
The integer divide instruction divides the two source registers and
stores the result in the destination register. This instruction can take
from 1 - 20 cycles to complete execution. The execution time is
selectable by the user.
INT_Load(dest, offset, src1)
The integer load instruction uses an integer value stored in source
register # 1 and an offset to compute the memory address from which data
will be loaded into the destination register. This instruction takes 1
cycle during the execution stage to compute the memory address. The
value from memory is available after the MEM stage. It is assumed that
the requested data is always available in the data cache so that the
pipeline will never have to stall while data is read from the memory.
INT_Store(src1, offset, src2)
The integer store instruction uses an integer value stored in source
register # 2 and an offset to compute the memory address to which the
data in source register # 1 will be stored. This instruction takes 1
cycle during the execution stage to compute the memory address. The
value is written to memory by the end of the MEM stage. It is assumed
that the data to be written to memory is already available in the data
cache so that the pipeline will never have to stall while data is
written to memory. This instruction does not go through the WB stage.
BR_Taken(offset, src1)
The branch taken instruction uses an integer value stored in source
register #1 and an offset to compute the branch target memory address.
This instruction assumes that the branch condition evaluates to "TRUE."
Thus if there is an instruction immediately following this instruction
in the pipeline, it must be canceled. It is assumed that the branch
target address and the branch condition evaluation can be determined by
the end if the ID stage. Thus this instruction never enters the EX stage.
BR_Untaken(offset, src1)
The branch untaken instruction uses an integer value stored in source
register #1 and an offset to compute the branch target memory address.
This instruction assumes that the branch condition evaluates to "FALSE."
Thus if there is an instruction immediately following this instruction
in the pipeline, it will continue to execute without any problems. It is
assumed that the branch target address and the branch condition
evaluation can be determined by the end if the ID stage. Thus this
instruction never enters the EX stage.
Structural Units
This simulation contains 6 structural units that can cause a structural
hazard.
1. Floating Point Add/Subtract Unit.
2. Floating Point Multiply Unit.
3. Floating Point Divide Unit.
4. Integer Add/Subtract Unit.
5. Integer Multiply Unit.
6. Integer Divide Unit.
Note: The load and store instructions use the Integer Add/Subtract Unit
to compute the memory address. Therefore, a floating-point load or store
can be stalled by a floating-point add or subtract that takes longer
than one cycle to complete.
Using the Application
The application loads into two frames. Initially, the bottom frame will
be empty.
Top Frame
The top frame allows the user to enter and remove instructions from the
pipeline. It also allows the user to set the execution time for several
of the instructions and to enable or disable data forwarding.
Adding an Instruction
To add an instruction to the pipeline, the user first selects the name
of the instruction they would like to add from the dropdown box. Once
the name of the instruction has been selected, the user can select the
registers they would like to associate with this instruction following
the Assembly Instruction format. When the registers have been selected,
the user should click the "Insert Instruction" button. This will cause
the current state of the pipeline to appear in the bottom frame. The
user can continue entering instructions repeating this procedure at any
time.
Removing an Instruction
In the event that a user makes a mistake when entering an instruction
into the pipeline, the last instruction can always be removed from the
pipeline by clicking on the "Remove Instruction" button.
Data Forwarding
Data forwarding can be enabled by placing a checkmark in the "Data
Forwarding" checkbox. Data forwarding can be disabled by removing the
checkmark from the "Data Forwarding" checkbox. Whenever this value is
changed, the bottom frame is updated to reflect the new state of the
pipeline.
Resetting the Application.
The application can be reset at any time by clicking on the "Reset
Application" button.
Help
This help page can be accessed at any time by clicking on the "Help" button.
Setting the Instruction Execution Time
There are 4 functional units for which the execution time can be
modified by the user. To change the execution time for a particular
functional unit, select the dropdown box next to the functional until
and select the number of cycles that the functional unit should take to
complete an operation. Whenever an execution time is changed, the bottom
frame is updated to reflect the new state of the pipeline.
Bottom Frame
The bottom frame is divided into two sections. The upper section shows
the instructions in the pipeline and what stage each instruction is in
as it is executed. The lower section is used to list the potential
structural and data hazards.
Stepping Through the Instructions
The user can step through the instructions in the pipeline one cycle at
a time by clicking on the "Step" button repeatedly.
Executing All Instructions
The user can execute all instruction to completion in one step by
clicking on the "Execute All Instructions" button.
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